1. Field of the Invention
The present invention relates to a clock/data recovery circuit using a voltage control oscillator which generates a clock signal of a frequency corresponding to 1/K (K=2, 3 , . . . ) of bit rate of an input data signal.
2. Description of the Related Art
The clock/data recovery circuit is applied to a receiver part and the like of an optical front end circuit in a router or a cross-connect switch of point to point transmission, GbE/10GbE, Fibre Channel in an optical communication system.
FIG. 1 shows a configuration of a conventional clock/data recovery circuit. This configuration is a PLL configuration using the voltage control oscillator which outputs a clock signal of a frequency of 1/2 of bit rate of an input data signal (refer to: M. Wurzer, et. al., “A 40-Gb/s Integrated Clock and Data Recovery Circuit in a 50-GHz Silicon Bipolar Technology,” IEEE J. Solid-State Circuits, VOL. 34, NO. 9, pp. 1320–1324 September 1999).
This clock/data recovery circuit includes a voltage control oscillator (VOC) 51 which outputs a clock signal CLK1 at a frequency of 1/2 of bit rate of an input data signal DIN, D-type ms-flip flop circuits (DFF) 52 and 53 (which write data at a rising edge), a 90-degree delay circuit 54 which delays phase of a signal by 90-degree, a D-type ms-flip flop circuit 55 which receives a clock signal CLK2 output from the 90-degree delay circuit 54, an EXOR circuit 56 which compares phases of signals D2 and D3 output from D-type ms-flip flop circuits 53 and 55, a lowpass filter (LPF) 57 which extracts DC voltage from the phase compared signal output from the EXOR circuit 56 and inputs the DC voltage to the voltage control oscillator 51 as a control voltage. D1 is an output signal of the D-type ms-flip flop circuit 52.
FIG. 2 shows a timing chart of the signals DIN, D2, CLK1, CLK2 of the clock/data recovery circuit. (a), (b), (c) indicate a lock status, a lead status of the clock signal CLK1 and a lag status of the clock signal CLK1 respectively.
In the lock status shown in FIG. 2(a), the rising/falling edge of the clock signal CLK1 becomes the same timing as a center between edges of the input data signal DIN, and the rising/falling edge of the clock signal CLK2 becomes the same timing as an edge of the input data signal DIN.
When there are data transitions (1→0, 0→1) in the input data signal DIN, the EXOR circuit 56 outputs an output signal according to lead/lag relationship of the phase of the input data signal DIN and the clock signal CLK1.
In the case that there are transitions between data A and data B of the input data signal DIN, in the status of clock lead shown in FIG. 2(b), both of the D-type ms-flip flop circuits 53, 55 discriminates data A, so that the output signals D2 and D3 become the same sign. On the other hand, in the lag status shown in FIG. 2(c), since the D-type ms-flip flop circuit 53 discriminates data A and the D-type ms-flip flop circuit 55 discriminates data B, the sign of the output signals D2 and D3 becomes different.
Therefore, when there are data transitions in the input data signal DIN, the output signal of the EXOR circuit 56 is determined according to lead/lag status of the clock signal CLK1 with respect to the input data signal DIN. Then, a DC signal obtained by extracting DC voltage from the output signal by the lowpass filter 57 is input to the voltage control oscillator 51 as the feedback signal.
Accordingly, a clock/data recovery circuit which can perform pull-in by using the voltage control oscillator having an oscillation frequency of a half of an oscillation frequency of a voltage control oscillator of a clock/data recovery circuit using PLL can be realized.
However, FIG. 2(a) represents a timing chart of the ideal lock status. The edge of the clock signals CLK1 and CLK2 of FIG. 1 in an actual lock status repeats, as shown in FIG. 3(a), lead/lag movement with respect to the phase of the input data signal DIN around the pulse center t1 and the edge t2 of the input data signal DIN.
Assuming that the number of transitions of the input data signal DIN (the number of changes 1→0 or 0→1) for a time unit is NTR, the number of cases that phases of the clock signals CLK1, CLK2 are in the lead status for the input data signal DIN is NLEAD, and the number of cases that the phases are in the lag status is NLAG (=NTR-NLEAD), and the ratio of the lead/lag status number is RLL, RLL can be represented as RLL=NLEAD/NLAG (1). Accordingly, the ratio of the number of cases that the output of the EXOR circuit 56 is 1 to the number of cases that the output of the EXOR circuit 56 is 0 is determined, so that the output voltage of the lowpass filter 57 which is fed back to the voltage control oscillator 51 can be determined.
Assuming that free-running frequency of the voltage control oscillator 51 is fo(Hz) and the bit rate of the input data signal DIN is Br[b/s], the feedback voltage to the voltage control oscillator 51 in the lock status is in proportion to the difference fd between 2fo and Br. Therefore, the ratio of 1/0 of the output signal of the EXOR circuit in the lock status is in proportionate to fd. As a result, a relationship RLL∝fd holds true.
Although the ratio RLL of the lead/lag status number is determined by feeding a voltage proportionate to fd back to the voltage control oscillator 51, the phase difference (the magnitude of lead/lag) is not decided. That is, there may be a case in which RLL is the same and the phase magnitude of each lead/lag status is different (FIG. 3(b), (c)). FIG. 3(b) shows a case when the magnitude of lead/lag is small and FIG. 3(c) shows a case when the amount of lead/lag is large.
In FIG. 3(b), (c), even when RLL is the same and the feedback voltage to the voltage control oscillator 51 becomes the same, clock jitter in FIG. 3(c) is larger since the phase magnitude is different. In the status that the feedback voltage to the voltage control oscillator 51 becomes the same, the range of clock phase change in each lead/lag is ±90-degree. That is, when the bit rate of the input data signal DIN is BR[b/s]and α is jitter [s]pp due to noise generated in the component, the jitter can be represented as1/(BR)+α[s]pp  (3)Thus, there is a large problem in that large jitter is generated.
Another example of the conventional CDR (Clock and Data Recovery), as shown in FIG. 4, is one using VCO having the same oscillation frequency as the input data bit rate. This CDR circuit extracts a clock signal CLK from the input data signal DATAIN, discriminates data signal. By adding a demultiplexer (DEMUX) and by inputting CDR clock output and data output into the DEMUX, the DEMUX outputs low speed parallel data signals demultiplexed of serial data signal output from CDR. Compared with the first conventional CDR, according to this configuration, the operation speed required for VCO becomes double and there is a problem in that speedup becomes difficult.